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FPGA

FPGA — FPGA Engineer

Applications open

Design and implement the low-latency hardware that forms the core of QTE's FPGA trading system. Depending on your team, you may work on market-data processing, order books, matching logic, pricing, trading signals, order generation or execution. You will work closely with your Team Lead, other FPGA Engineers and the team's Software Engineer.

What you'll do

Arm: FPGA · Places: 3 per team · Team size: 5

About QTE

Queen's Tower Exchange is a financial-markets simulation for Imperial College London students. The FPGA Trading Project develops low-latency electronic trading systems across three teams: Exchange, Market Making and Market Taking.

The FPGA Trading Project consists of three teams — Exchange, Market Making and Market Taking — with five students in each team. Each team will have 1 Team Lead, 3 FPGA Engineers and 1 Software Engineer.

Applicants will be placed into teams based on their interests, technical strengths and where they are likely to contribute most effectively. Previous quantitative-finance or trading experience is not required. Applications are open to students from all disciplines, excluding first-year undergraduates.

Responsibilities

  • Design and implement RTL using SystemVerilog/Verilog.
  • Translate algorithms and system requirements into FPGA architectures.
  • Develop pipelined, low-latency hardware components.
  • Work on functionality such as market-data processing, order-book logic, matching, pricing, signals or execution depending on team allocation.
  • Test, debug and validate FPGA modules.
  • Analyse latency, throughput and hardware-resource usage.
  • Work with C++ and Python reference models to check hardware behaviour.
  • Collaborate with other engineers on interfaces and system integration.
  • Document technical decisions and communicate problems clearly to the team.

What success looks like

Reliable FPGA components that behave correctly, meet agreed interfaces and integrate cleanly with the wider trading system. Strong engineers will produce clear, testable designs, communicate technical issues early and continuously improve the latency, efficiency and robustness of their implementation.

Prerequisite knowledge

  • Experience in SystemVerilog or Verilog and in C++ and Python.
  • Relevant experience may be demonstrated through coursework, personal projects, university projects, research or previous technical experience.
  • Strong problem-solving and analytical skills.
  • Ability to learn new concepts and technologies quickly.
  • Good communication and teamwork skills.
  • A genuine interest in quantitative finance, electronic trading and financial markets.
  • Ability to commit consistently to the project.

An industrial internship, UROP or previous quantitative-finance internship is not required.

Useful, but not required

Experience with FPGA toolchains, digital design, computer architecture, pipelining, networking, embedded systems, hardware verification, financial market data or order-book projects.

What you'll be taught

Much of your learning will take place through project training, technical guidance and hands-on implementation.

  • How electronic markets, order books and execution systems operate.
  • How QTE's Exchange, Market Making and Market Taking systems interact.
  • How to map quantitative algorithms onto low-latency FPGA hardware.
  • How to optimise designs for latency, throughput and resource utilisation.
  • How to integrate FPGA modules into a larger hardware/software system.